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-- Company: 
-- Engineer: 
-- 
-- Create Date:    12:24:03 03/03/2012 
-- Design Name: 
-- Module Name:    dataMem - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.definitions.all;
use work.hdata.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity io is

generic (
			bits: integer := 8;
			ioSize: integer := 256
			);
			
port (	
		clk_i : in STD_LOGIC;
		port_cyc_i : in STD_LOGIC;
		port_stb_i : in STD_LOGIC;
		port_we_i : in STD_LOGIC;
		port_ack_o : out std_logic;
		port_addr_i : in std_logic_vector(7 downto 0);
		port_word_i : in std_logic_vector(7 downto 0); 		
		port_word_o : out std_logic_vector(7 downto 0);
		int_req_o: out std_logic;
		int_ack_i: in std_logic
);

end io;

architecture Behavioral of io is

		
		signal read_ack:STD_LOGIC:='0';
		signal write_ack:STD_LOGIC:='0';
		
begin

	process(clk_i) is

	begin
		if (rising_edge(clk_i)) then
			if (port_stb_i = '1' and port_cyc_i = '1') then
				if (port_we_i = '1') then
					--io_memory(conv_integer(port_addr_i)) <= port_word_i;	
					write_ack<='1';
					read_ack<='0';
				else
					--port_word_o <= io_memory(conv_integer(port_addr_i));
					read_ack<='1';
					write_ack<='0';
				end if;
			else
				write_ack<='0';
				read_ack<='0';
			end if;	
		end if;
		
	end process;
	
	port_ack_o <= port_stb_i and port_cyc_i and (write_ack or read_ack);

end Behavioral;
